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Physical Verification Lead


  • Hands on experience with leading Physical Verification activities at fullchip level in multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm)
  • Lead PV activities on SoC designs with expertise in DRC, LVS, DFM, HV checks and cleanup
  • Expertise in running PV checks on Flat/Hierarchical SoC designs with multiple power domains
  • Excellent understanding of DPT, DFM , DFY, Flipchip checks in lower technology nodes
  • Work closely with PD team to define methodology to address PV issues during PnR
  • Work closely with CAD teams and involve in methodology development and improvement
  • Own SoC PV activities while managing a team of 5-10 engineers

Desired Skills and Experience:

  • The candidate should be able to work with and lead a team of engineers working on PV closure on SOC designs
  • Should have handled Synthesis/STA for atleast 2-3 SoC designs on lower technology nodes
  • Excellent understanding of PV rules viz. Antenna, Density, DFM, DFY, DPT at lower technology nodes
  • Ability to setup PV flows viz. DRC, LVS, Fill insertion and proficiency in script based design cleanup
  • Experienced in industry standard tools viz. ICV, Calibre, PVS
  • Package PV checks, IO/Bump PV cleanup understanding is a plus
  • Knowledge in TCL, Perl scripting is a plus
  • Experience: 5-10 years