Front end Implementation Engineer (Synthesis)
You will be part of Front End Team where you will be accountable for Fullchip Timing Closure. Working / leading Fullchip Timing unconstraints endpoints and no clock issues, Timing synchronizer Failure rate. Work Closely with Design team to resolve timing related issues.
Desired Skills and Experience:
- Complete hands-on experience Static Timing Analysis
- Experience in Fullchip Timing will be a plus
- Worked on Low Power Techniques – Multi Mode Multi Corner, POCV
- Strong Communication skills
- You should have hands on experience on Static Timing Analysis and Timing closure.
- Expert in prime time.
- Efficient communication skills to interface with Back End Design team
- or RTL Designers to resolve Design Issues
- Expertise in using Prime Time suit
- Experience in Tcl/Tk, PERL, Makefile is a Plus
- Experience: 3+ years