- Work closely with designers and CAD engineers to develop, support, and document custom design CAD tools and flows in areas such as static timing analysis, extraction, cell characterization, design checks, electro-migration, logical equivalency, flow automation, and publishing.
- The tools and flows are implemented in languages, such as perl and python and utilize commercial tools from major CAD vendors (Synopsys, Cadence, Mentor, and Ansys).
- Excellent communication skills are needed to work across geographic and design team boundaries.
- Design knowledge is required to understand requirements, debug flow issues, and suggest methodology changes.
Desired Skills and Experience:
- Good VLSI design and CAD experience with at least a Bachelors & 3+ Years or MS degree
- Preferred knowledge of signal integrity, timing flows, and circuit design concepts
- Coding experience with object-oriented techniques in Perl are required along with experience using TCL
- Some experience with commercial tools for LVS, extraction, characterization, static timing, design entry, and EMIR analysis is preferred.