INVECAS Inc. - Verification Engineer

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Desired Skills and Experience:

Strong in OVM/UVM verification methodology
Developing Detailed Test plan including Test algorithms from the Spec
Identify corner case scenarios for thorough verification.
Develop Test bench/its components, Test Stimulus & Ability to resolve issues quickly, Offer solutions for automation.
Strong debugging skills, problem solving skills. Identify and address the root cause of bugs
Good understanding on assertion based verification and functional and code coverage
Solves complex problems with some direction and makes amends to standard methodology or practices
Drive collaborative solutions for issues, methodologies and processes related to inter or intra-organization
Experience: 4-6 years

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IP/SOC design engineer working in the area of micro architecture, logic design, RTL coding, verification, supporting validation/software, silicon implementation support activities (ex: synthesis, timing, DFT, p&r)

Desired Skills and Experience:

3+ years of hands-on experience with SoC design
Worked on DDR/LPDDR/PCI Express/USB 2.0,3.0 protocols
experience with MCU and APU class processors
experience with AXI/AHB or other standard on-chip buses
Good knowledge of processor based SoC architecture
Excellent debugging skills
Broad understanding of RTL-to-Tapeout methodology
Prior experience with pre and post silicon debug
Prior experience with QSPI, PSRAM, low power implementations
Hands-on experience with Synthesis and Logic Equivalency checking
Hands-on experience with FPGA debug
Experience with Verilog/PSL/OVA assertions
BTech/MTech in EE or equivalent with 3-7 years of experience
Outstanding analytical and critical thinking skills.
Be a good contributor to the organization & a team player

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Hands on experience with Power and EMIR analysis of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm)
Lead EMIR activities with expertise in Power/Signal EM, Static and Dynamic Power/IR
Expertise in Flat/Hierarchical SoC design IR. To create models for tiles and blocks as required.
Expertise in ESD/CDM/HBM for ensuring Resistance limits for different aspects of PG.
Work closely with CAD teams and develop flows for different customers of Invecas.
Own EMIR activities onsite/offsite as required, while managing a team of 3-5 engineers

Desired Skills and Experience:

B. Tech. / M. Tech. with 5-10 years of experience in EMIR, ESD
The candidate should be able to work with and lead a team of engineers.
Should have strong technical experience in Power, IR, ESD, EM.
Basic understanding of PD and STA flows.
Excellent debugging capabilities; to help PD team in achieving quick design closure
Experienced in industry standard tools viz. RH, Totem, Voltus, Voltus-fi, Bluewave etc.
Knowledge in TCL, Perl scripting is a must

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Hands on experience with leading Physical Verification activities at fullchip level in multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm)
Lead PV activities on SoC designs with expertise in DRC, LVS, DFM, HV checks and cleanup
Expertise in running PV checks on Flat/Hierarchical SoC designs with multiple power domains
Excellent understanding of DPT, DFM , DFY, Flipchip checks in lower technology nodes
Work closely with PD team to define methodology to address PV issues during PnR
Work closely with CAD teams and involve in methodology development and improvement
Own SoC PV activities while managing a team of 5-10 engineers

Desired Skills and Experience:

The candidate should be able to work with and lead a team of engineers working on PV closure on SOC designs
Should have handled Synthesis/STA for atleast 2-3 SoC designs on lower technology nodes
Excellent understanding of PV rules viz. Antenna, Density, DFM, DFY, DPT at lower technology nodes
Ability to setup PV flows viz. DRC, LVS, Fill insertion and proficiency in script based design cleanup
Experienced in industry standard tools viz. ICV, Calibre, PVS
Package PV checks, IO/Bump PV cleanup understanding is a plus
Knowledge in TCL, Perl scripting is a plus
Experience: 5-10 years

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Hands on experience with Implementation (PnR & Signoff) of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm)
Lead all aspects of SoC Physical Design with strong expertise in the area of chip/partition floor-planning, design partition creation, budgeting and feedthrough planning
Work alongside RTL/Synthesis/DFT teams to define design partitions and create floorplan as per the design data flow
Work closely with library, technology and Analog IP teams for physical design requirements
Work closely with CAD teams and involve in methodology development and improvement
Own SoC/partition physical design activities while managing a team of 4-5 engineers

Desired Skills and Experience:

B. Tech. / M. Tech. with 5-12 years of experience in Physical Design
The candidate should be able to work with and lead a team of engineers on all aspects of Physical Design tasks on an SOC design
Should have handled Netlist to GDS II implementation at Chip/partition level for atleast 2-3 designs
Hands-on expertise with technology nodes like 28nm, 16nm and below
Good knowledge of EDA tools from Synopsys, Cadence and Mentor, particularly with ICCII & Calibre
Excellent understanding of design partitioning & budgeting along with hands-on experience in Chip/partition floor planning, placement optimizations, Clock planning and routing.
Good understanding of low power implementation techniques and static low power checks
IO ring design and bump planning is a plus
Being proficient in TCL, Perl scripting is a plus

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Responsible for creating digital IP to enable layout work in new technology: PCELL creation, SRAM leaf cells, Productivity Scripts.
Responsible for analysis of new technology and translating into guidelines for EMIR, SRAM layout guidelines etc.
Review layouts for area/power/quality and post layout activities.
Experience in handling of different types of memory architecture.
Power and signal route planning.
Block and top level layouts, integration and validations.
Floor plan and integration of major layout modules.

Desired Skills and Experience:

You would need to have sound fundamentals in CMOS devices, basics of VLSI design.
Proven project cycle and tape out experience in SRAM memory layout design.
Proficiency in Perl/Python or equivalent scripting language.
Good interpersonal skills, should be an excellent teammate.
BE/M-Tech in Electrical & Electronics or equivalent.

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Full custom circuit design involving memory arrays like multi-port register files, SRAMs, and/or caches, for performance critical IPs like CPUs/GPUs.
Design cutting-edge SRAM circuits using state-of-the-art technology processes
Optimize circuits for performance, area, and power
You will have to perform transistor level circuit and logic design, spice verification, schematic entry and coordination with layout team.
Ability to understand architectural specifications and develop custom SRAM circuits which meet stringent performance, area and power requirements.
Ability to close design to the specs by running various flows like EM, IR, Noise, static timing analysis.
Develop state of the art flows for timing, EM/IR or other verification needs.
Improve/develop flows, methodologies and automation to accelerate various design closure, data collection, and analysis, further ensure working silicon

Desired Skills and Experience:

You would need to have sound fundamentals in CMOS devices, basics of VLSI design.
Prior experience is required with hspice simulations, variation analysis and transistor level design.
Proficiency in Perl/Python or equivalent scripting language is a requirement.
Prior exposure to some form of memory design (like SRAMs or register files) will be a huge advantage.
Good interpersonal skills, should be an excellent teammate.
BE/M-Tech in Electrical & Electronics or equivalent.

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Desired Skills and Experience:

Engineer should have experience of 2+ years.
Should have good knowledge of CMOS circuit layout Fundamentals, Technology Effects, Matching concepts.
Should have the ability to analyze and debug issues related to layout design like DRC, LVS, ERC etc.
Should have good knowledge of latch-up, ESD, EMIR and PERC
Should have the ability to work on top level and power mesh
Need to develop layouts for GPIO, LVDS, I2C/I3C.

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Desired Skills and Experience:

Recent experience in I/O designs on lower technology nodes.
Solid understanding of related CMOS and FinFET process technology issue.
Familiar with I/O design methodology & flow.
Familiar with signal switching, noise & design issues.
Knowledge of aging and reliability concepts
Knowledge of esd related concepts.
Good communication skills and ability to work across multiple teams in multiple locations.
2+ years of experience.

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Hands on experience with Timing Analysis of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm)
Lead STA activities on SoC designs with expertise in Constraints creation, CDC checks and Pre/Post Layout Timing closure
Expertise in Timing constraints creation for FE/BE, time budgeting, constraints coverage analysis, Timing closure techniques in MMMC environment
Work closely with CAD teams and involve in timing methodology development and improvement
Own SoC timing activities while managing a team of 5-10 engineers

Desired Skills and Experience:

B. Tech. / M. Tech. with 5-10 years of experience in STA
The candidate should be able to work with and lead a team of engineers working on Timing closure for SOC design
Should have handled STA for at least 2-3 SoC designs on lower technology nodes
Excellent understanding of timing closure techniques & SI analysis/fixes in lower technology nodes in high-speed designs with DDR, Serdes, USB interfaces
Experienced in industry standard tools viz. Synopsys PT, Cadence Tempus
Knowledge in TCL, Perl scripting is a must