Qualification: B.Tech / M.Tech with 5-12 years of relevant experience
Strong experience in Pre Silicon Emulation & demonstrable experience using ZEBU Emulators
Strong experience in SOC level Verification & demonstrable experience in VCS Simulators
Strong expertise and verification experience in the areas of
SOC/GPU Architecture
PCIe
Memory Controllers
Graphics IP
Strong in key DV Skillset – Verilog/SV/UVM skills, Testplans, Testbench & Test stimulus development, Coverage aspects.
Strong debugging skills, problem solving skills. Identify and address the root cause of bugs independently, offer solutions for automation.
Drive collaborative solutions for issues being a quick learner, being flexible and adaptable with right interpersonal skills and work well in the intra or inter-organization team setup
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Desired Skills and Experience:
4-6 years of relevant experience
Strong in OVM/UVM verification methodology
Developing Detailed Test plan including Test algorithms from the Spec
Identify corner case scenarios for thorough verification.
Develop Test bench/its components, Test Stimulus & Ability to resolve issues quickly, Offer solutions for automation.
Strong debugging skills, problem solving skills. Identify and address the root cause of bugs
Good understanding on assertion based verification and functional and code coverage
Solves complex problems with some direction and makes amends to standard methodology or practices
Drive collaborative solutions for issues, methodologies and processes related to inter or intra-organization
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Hands on experience with leading Physical Verification activities at fullchip level in multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm)
Lead PV activities on SoC designs with expertise in DRC, LVS, DFM, HV checks and cleanup
Expertise in running PV checks on Flat/Hierarchical SoC designs with multiple power domains
Excellent understanding of DPT, DFM , DFY, Flipchip checks in lower technology nodes
Work closely with PD team to define methodology to address PV issues during PnR
Work closely with CAD teams and involve in methodology development and improvement
Own SoC PV activities while managing a team of 5-10 engineers
Desired Skills and Experience:
5-10 years of relevant experience
The candidate should be able to work with and lead a team of engineers working on PV closure on SOC designs
Should have handled Synthesis/STA for atleast 2-3 SoC designs on lower technology nodes
Excellent understanding of PV rules viz. Antenna, Density, DFM, DFY, DPT at lower technology nodes
Ability to setup PV flows viz. DRC, LVS, Fill insertion and proficiency in script based design cleanup
Experienced in industry standard tools viz. ICV, Calibre, PVS
Package PV checks, IO/Bump PV cleanup understanding is a plus
Knowledge in TCL, Perl scripting is a plus
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Hands on experience with Implementation (PnR & Signoff) of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm)
Lead all aspects of SoC Physical Design with strong expertise in the area of chip/partition floor-planning, design partition creation, budgeting and feedthrough planning
Work alongside RTL/Synthesis/DFT teams to define design partitions and create floorplan as per the design data flow
Work closely with library, technology and Analog IP teams for physical design requirements
Work closely with CAD teams and involve in methodology development and improvement
Own SoC/partition physical design activities while managing a team of 4-5 engineers
Desired Skills and Experience:
B. Tech. / M. Tech. with 5-12 years of experience in Physical Design
The candidate should be able to work with and lead a team of engineers on all aspects of Physical Design tasks on an SOC design
Should have handled Netlist to GDS II implementation at Chip/partition level for atleast 2-3 designs
Hands-on expertise with technology nodes like 28nm, 16nm and below
Good knowledge of EDA tools from Synopsys, Cadence and Mentor, particularly with ICCII & Calibre
Excellent understanding of design partitioning & budgeting along with hands-on experience in Chip/partition floor planning, placement optimizations, Clock planning and routing.
Good understanding of low power implementation techniques and static low power checks
IO ring design and bump planning is a plus
Being proficient in TCL, Perl scripting is a plus
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Work closely with designers and CAD engineers to develop, support, and document custom design CAD tools and flows in areas such as static timing analysis, extraction, cell characterization, design checks, electro-migration, logical equivalency, flow automation, and publishing.
The tools and flows are implemented in languages, such as perl and python and utilize commercial tools from major CAD vendors (Synopsys, Cadence, Mentor, and Ansys).
Excellent communication skills are needed to work across geographic and design team boundaries.
Design knowledge is required to understand requirements, debug flow issues, and suggest methodology changes.
Desired Skills and Experience:
Good VLSI design and CAD experience with at least a Bachelors & 3+ Years or MS degree
Preferred knowledge of signal integrity, timing flows, and circuit design concepts
Coding experience with object-oriented techniques in Perl are required along with experience using TCL
Some experience with commercial tools for LVS, extraction, characterization, static timing, design entry, and EMIR analysis is preferred.
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Hands on experience with Power and EMIR analysis of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm)
Lead EMIR activities with expertise in Power/Signal EM, Static and Dynamic Power/IR
Expertise in Flat/Hierarchical SoC design IR. To create models for tiles and blocks as required.
Expertise in ESD/CDM/HBM for ensuring Resistance limits for different aspects of PG.
Work closely with CAD teams and develop flows for different customers of Invecas.
Own EMIR activities onsite/offsite as required, while managing a team of 3-5 engineers
Desired Skills and Experience:
B. Tech. / M. Tech. with 5-10 years of experience in EMIR, ESD
The candidate should be able to work with and lead a team of engineers.
Should have strong technical experience in Power, IR, ESD, EM.
Basic understanding of PD and STA flows.
Excellent debugging capabilities; to help PD team in achieving quick design closure
Experienced in industry standard tools viz. RH, Totem, Voltus, Voltus-fi, Bluewave etc.
Knowledge in TCL, Perl scripting is a must
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Design and development of layouts for analog and mixed signal IPs including IOs, BangGap, linear and switching voltage regulators, PLLs, Sensors, XTAL Oscillators, RC-Oscillators, ADC, DAC etc.)
Responsible for Block level/top level layout implementation meeting design constraints
Strong focus on automation/Scripting to improve the time to design
Planning and layout execution as per project requirements
Desired Skills and Experience:
B.E/B.Tech in Electronics with 3-8 years of relevant experience
Good understanding of CMOS and FinFet technologies (device physics, deep sub-micron effects and layout effects)
Proficient in EDA tools used for layout design (e.g. Virtuoso/OA for layout design – L/XL/GXL, Calibre for DRC/LVS/DFM, StarRC/QRC for Extraction, tools for Electro-migration and IR Drop analysis)
Good understanding of Design Rule Manual and Design Rules
Good understanding of Analog Layout fundamentals (e.g. Matching, Electro-migration, Latch-up, coupling, cross-talk, IR-drop, active and passive parasitic devices etc.)
Ability to understand design constraints and implement high quality layouts accordingly
Technical trouble-shooting and demonstrated problem solving skills
Team player, flexible, good communication skills
Good understanding of usage of standard cells in P & R and proficiency in P & R flow is desirable
Scripting language (SKILL/Perl/TCL) proficiency is also desirable
Provide reasonably accurate estimates of timescales for work.
Hands on experience with DFT of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 14nm)
Should have experience in DFT and ATPG activities on SoC designs with expertise in MBIST Planning/Insertion, Partitioning Design for Scan, Scan Insertion,
Compression, Wrapper Insertion, ATPG Simulations
Expertise in handling Flat/Hierarchical SoC designs
Expertise in JTAG, Boundary Scan, STA Constraints creation for DFT modes
Desired Skills and Experience:
B. Tech. / M. Tech. with 5-12 years of relevant experience
The candidate should be able to work with and lead a team of engineers
Should have worked on full chip DFT activities for atleast 2-3 SoC designs
Experienced in industry standard tools viz. Mentor/Cadence
Knowledge in TCL, Perl scripting is preferable
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To develop advanced ΔΣ, SAR, Pipelined ADCs, DAC / PLL, Crystal Oscillator / Voltage regulator / General purpose and Special IO solutions
Analog IP development either leading a team or as individual contributor
Complete Analog Design flow (specs, architecture definition, spice simulations, layout supervision, IP integration, etc.)
Support to Validation, SoC Applications teams and to end customers
Driving innovation and develop new architectures for best-in-class solution
Coaching and mentoring junior design engineers
Desired Skills and Experience:
M.S./M.Tech/B.E./B.Tech (Electronics) with 3-5 years relevant experience
Experience of working on advanced analog and AMS designs (ADC, DAC/PLL/Oscillator/Voltage Regulators/IOs) with full ownership from specifications to silicon
Strong fundamental knowledge for AMS design, Advanced CMOS, FDSOI and FinFet technologies
Technical troubleshooting and demonstrated problem solving skills
Team player, flexible, good communicator
Active involvement in problem solving and implementing opportunities for improvement.
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