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Power Signoff Lead

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  • Hands on experience with Power and EMIR analysis of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm)
  • Lead EMIR activities with expertise in Power/Signal EM, Static and Dynamic Power/IR
  • Expertise in Flat/Hierarchical SoC design IR. To create models for tiles and blocks as required.
  • Expertise in ESD/CDM/HBM for ensuring Resistance limits for different aspects of PG.
  • Work closely with CAD teams and develop flows for different customers of Invecas.
  • Own EMIR activities onsite/offsite as required, while managing a team of 3-5 engineers

Desired Skills and Experience:

  • B. Tech. / M. Tech. with 5-10 years of experience in EMIR, ESD
  • The candidate should be able to work with and lead a team of engineers.
  • Should have strong technical experience in Power, IR, ESD, EM.
  • Basic understanding of PD and STA flows.
  • Excellent debugging capabilities; to help PD team in achieving quick design closure
  • Experienced in industry standard tools viz. RH, Totem, Voltus, Voltus-fi, Bluewave etc.
  • Knowledge in TCL, Perl scripting is a must