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GPIO Layout Engineer


Desired Skills and Experience:

  • Engineer should have experience of 2+ years.
  • Should have good knowledge of CMOS circuit layout Fundamentals, Technology Effects, Matching concepts.
  • Should have the ability to analyze and debug issues related to layout design like DRC, LVS, ERC etc.
  • Should have good knowledge of latch-up, ESD, EMIR and PERC
  • Should have the ability to work on top level and power mesh
  • Need to develop layouts for GPIO, LVDS, I2C/I3C.