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Front end Implementation Engineer (Synthesis)/LINT/CDC


Responsible for Synthesis Constraints development, LINT checks, CDC checks. Working / leading full-chip STA closure, defining mode requirements & corners for timing closure. Formal Verification-Synopsys Formality. You will be working on low power designs. Work Closely with Physical Design team to resolve any timing related issues with 3+ years of experience.

Desired Skills and Experience:

  • Should have hands on experience on RTL to GDS Synopsys flow. Include all aspects of physical design including physical Implementation, Timing closure (Complete QOR).
  • Expert knowledge of Synopsys IC-Compiler and proficient and powerful user of Synopsys Tool Suite DC/ICC/Star/PT).
  • Efficient communication skills to interface with Back End Design team or RTL Designers to resolve Design Issues.
  • Complete hands-on experience over Clock Domain Crossing/LINT/ Synthesis, Timing Closure and Static Timing Analysis
  • Expertize in Formal Verification- (Synopsys Formality)
  • Worked on Low Power Techniques – Clock/Power gating, Multi-Voltage designs etc.
  • Expert in STA Tools & Methodologies for Timing closure with good understanding of OCV, Noise, Cross-Talk effects on Timing, Timing Budgeting
  • Expertise in using Prime Time/Worked on Spyglass, Questa
  • Experience in Tcl/Tk, PERL, Makefile is a Plus