Digital Verification Lead
Bachelor/Master’s degree in Electrical/Electronics/Computer Engineering with an experience of 10-14 years
Desired Skills and Experience:
- Strong in Verification methodology involving OOPs concepts C++, UVM Methodology knowledge and experience
- Sound knowledge in SOC level verification. Good knowledge on directed, random, constrained random verification.
- Developing Detailed Test plan including Test algorithms from the Spec
- Develop Test bench/its components, Test Stimulus in Verilog, SystemVerilog, UVM or SystemC
- Strong hands-on debugging skills, problem solving skills. Identify and address the root cause of bugs
- Good understanding on assertion based verification, functional and code coverage
- Should be capable of independently driving tasks and activities to completion in an organized and timely manner with the right quality
- Strong knowledge on design & verification flows.
- Strong knowledge of C/C++, Perl script programming skills.
- Solves complex problems with some direction and makes amends to standard methodology or practices
- Drive collaborative solutions for issues, methodologies and processes related to inter or intra- organization
- Experience in technical mentoring and people management preferred.