Custom Application Engineer
- Need to evaluate the Alpha plan and test the deliverable releases accordingly.
- Need to validate the bug fixes and Enhancements of the corresponding IP releases.
- Need to automate the methodologies which eases the debug of the AE engineers.
- Evaluates and exercises various aspects of the development flow which may include RTL lint and CDC checking, functional simulation, constraint checking, design, synthesis, timing analysis.
- Develops and maintains common methodology documentation and flow
Required Skillset for AMBA, PCIE, USB, DDR and Ethernet CAE:
- Working knowledge of RTL design, synthesis and good understanding of ASIC design flow.
- Familiar with Synopsys synthesis, STA, formal verification, P&R and DFT tools is a plus.
- Application support experience is a plus, but not a must.
- Experience in IP or SoC verification
- Expert in developing test bench/test case using System Verilog & UVM
- Prior experience with code coverage, functional coverage & assertions is desired
- Knowledge on Shell, Perl and Python for scripting
- Must have good debugging and problem-solving skills
- Prior Experience of any of the below protocols:
- AMBA protocols – AHB, AXI and APB
- DDR Protocol — DFI Interface, DDR4, DDR5, LPDDR4 and LPDDR5
- USB 2 and USB 3 protocol
- Good communication skills
Required skillset for DDM:
- Good knowledge of Verilog RTL, IP deliverables, ASIC design flow.
- Familiarity with Synopsys tools (SpyGlass, VC Static, PrimeTime,DC) or any other similar tools
- Good knowledge and experience in developing timing constraints.
- Good scripting knowledge preferably tcl & perl.
- Good analysis and problem-solving skills
- Solid written and verbal communication skills and the ability to create clear and concise documentation.
- Working knowledge of high-speed interface protocols such as MIPI, PCIe, USB, and DDR is a plus
- Experience as Lead is a plus.