System Design & Validation
INVECAS System Engineering (SE) team has expertise in Pre-Silicon Emulation/Validation and complete Post Silicon activities for both SoC and IP designs. Before IP team acquisition, SE team handled most of the IP Post-Silicon activities, i.e, from Substrate/Platform design to Validation/Characterization/Certification. SE Team services include but are not limited to Substrate/Platform design, SI/PI, Emulation, IP/SoC Validation/Characterization activities. With a well-equipped lab, extensive design debug knowledge, automated infrastructure & elaborate test plans, the SE team will be an ideal partner to provide the best platform/test solutions in a competitive timeline.
Since the inception of INVECAS SE team, the following are a few of the accomplishments
- 100+ IP’s characterized (Includes re-spins)
- 20+ Characterization boards designed
- 10+ Validation boards designed
- 10+ Package Substrates designed
- 3 Xilinx FPGA based platforms designed
- Worked on getting USB, PCIe, MIPI, DDR, HDMI IP’s certified
- In-house developed infra tools to enable quick test development and execution cycle
- Experience in performing SI/PI for complex designs upto 25Gbps
- Design Debug capability of both electrical/protocol issues
- Have expertise in correlating Silicon results with design specifications
- Executed Pre & Post Silicon Validation for 2 automotive SoC’s and 1 Consumer SoC
Platform Engineering
Our Platform design team interacts with customers from the concept phase and provides various options to architect the solution. Upon finalizing the solution, the team will meticulously execute the design, layout, signal/power simulation stages to incubate the robust platform. We engage with proven vendors for fabrication and assembly requirements to ensure timely delivery with quality. Services provided under Platform Engineering are:
- Substrate Design for Wirebond and Flip-Chip designs
- High-speed boards designed up to 25G Serial and 4266MTs LPDDR4
- Signal/Power Integrity for the complete platform
- IP/SoC Validation/Characterization Platforms
- Xilinx FPGA based custom platforms
- Expertise in Cadence/Mentor toolchain for board design/layout
- Expertise in Cadence Sigrity, Mentor HyperLynx & ADS SI tools.
Emulation
INVECAS Emulation services include FPGA based solutions, FPGA prototyping, and design porting to Emulators. With the increase in the complexity of the designs, time to market and robustness of the product are significant challenges that continue to exist. Early software development platform to improve silicon bring-up/product delivery time and platform with real-time interfaces to resolve asynchronous/system level scenarios are hard to simulate but made possible with the FPGA platforms
- FPGA based solutions (Zynq 7000, Zynq MPSoC)
- FPGA based emulation (Predominantly Xilinx FPGAs)
- Mentor Veloce based emulation
Pre & Post Silicon Validation
With the increase in design complexity and Tape-out costs, affording a respin will impact the project or the profit margins. At INVECAS, we consider Pre-Silicon validation as a critical sign-off criterion in the Chip design cycle to ensure first-pass silicon success. Our robust testplans and scalable methodology allow us to port the validation suite on processor independent platforms in no time. System-level usecases, Randomization, Compliance, Interoperability tests in the testplan ensure high coverage. Tests are developed in API’s based structure and can be used for board validation and characterization. The following are some examples of services offered:
- Test plan documentation derived from architecture specification
- Test case development
- FPGA/Silicon Bring-up
- Feature level and Use case validation
- Power/performance measurements
- Debug/Failure Analysis
- Diagnostics/Production Tests for platform screening
Characterization
Complex SoC’s yield and robustness are directly related to the Silicon specification margin. With the variation and complexities involved due to the shrinking of technology node, a thorough understanding of the design margins is crucial. In characterization, Silicon is subjected to various environmental and test conditions to analyze the margins. With our well-equiped lab, automated test infrastructure, and experience, we can work with customers to articulate a testplan and execute meticulously. The test results are packaged into a silicon report highlighting the strength and weakness of the design along with recommendations on improvements for high yield/success rate. The following are some examples of services offered:
- Test plans & Automation development
- AC/DC Analysis
- IO/PLL Characterization
- INL/DNL for ADC/DAC’s
- JTOL for SERDES
- Receiver sensitivity tests
- Debug/Failure Analysis
- PVT analysis
- Power and leakage measurements
- Electrical compliance as per standards
IP’s Characterized
Analog Mixed Signal Interface IP:
- 25G SERDES targeted for PCIe Gen4 application
- 13G SERDES targeted for PCIe Gen3 and 10G Ethernet
- LPDDR3/4 upto 4266MTs
- HDMI 2.0/2.1 Tx/Rx
- DP2.0 Tx/Rx
- USB 2.0/3.0
- MIPI D-PHY targeting CSI-2, DSI-2
Analog IP:
- GPIO (Multiple IO standards like I2C/I3C, eMMC)
- PLL
- Thermal Sensor
- LVDS IO
- Back Bias Generator
- ADC/DAC
Lab
- ~4000sft area with ESD flooring audited quarterly
- 31 benches for use case level validation and overnight regressions
- 15 benches for electrical characterization
- 10 stations for PVT characterization capability to schmoo from -40 to 150C
- In-house Rework area for quick turn-around for experiments
Test & Measuring Equipment for High Speed Serial IO
- J-BERT M8020A, 33GHz
- Real Time Scope 33GHz, DSAQ93304A
- Wide Band Oscilloscope 50GHz, DCAX86100D
- Network Analyzer E5071C
- Signal Source Analyzer E5052B
- Pulse/Pattern Generators
- Logic Analyzer M9505A + U4154B
- DDR3/DDR4 DIMM Interposers (FS2361/2510A/2512)
- Low Bandwidth Oscilloscopes
- Bench Power Supplies, Multi Meters
- 10 Thermal Solution for PVT Testing
- In-house rework capability for all types of SMT Components